1. Field of the Invention
The present invention relates to a design method, a design program and a design support device for a semiconductor integrated circuit, which generates a cell library of a cell base semiconductor integrated circuit.
2. Description of Related Art
A cell base IC (Integrated Circuit) is suitably used in LSIs requiring high integration and high performance such as microprocessors and ASSPs (Application Specific Standard Product) as well as ASICs (Application Specific Integrated Circuit). The cell base IC is designed by combining user-original circuits. Here, the user-original circuits are designed by a user using a cell library supplied from semiconductor manufacturers. The cell library includes cells of various types and sizes ranging from a primitive cell that mounts a basic circuit therein to a macro cell that mounts a CPU and a memory therein. Since circuit design is performed by a placement and routing tool placing such cells on a chip, a design time and design costs can be reduced. Furthermore, since layout of a CPU and the like can be incorporated as a macro cell as it is, a system LSI can be easily created.
Layout of the cell base IC is created through a cell layout phase when the cell library is created and a chip layout phase when cells are placed on a chip by using the cell library. FIG. 1 is a flow chart showing a layout operation in a general chip layout phase. In the chip layout phase, the cells are placed on the chip on which a power wiring line is previously arranged by using a previously prepared cell library 100 (Step S101). Thereby, chip layout information 101 is generated. For example, chip layout shown in FIG. 2 is obtained.
FIG. 2 is a plan view showing an example of a layout structure of a semiconductor integrated circuit (chip). Referring to FIG. 2, in the semiconductor integrated circuit, a power wiring line 1, a power wiring line 2, and a power wiring line 3 are arranged. The power wiring line 1 is supplied with a power source voltage VDD and extends in a column direction (Y direction). The power wiring line 2 (power source voltage VDD) is connected to the power wiring line 1 and extends in a row direction (X direction). The power wiring line 3 (ground voltage GND) extends in parallel to the power wiring line 2. The power wiring line 2 supplies the source voltage VDD to cells 30 to 32 arranged in a region A in the row. The chip layout information 101 representing such a layout structure is recorded in a storage device (not shown).
Next, it is tested whether or not chip layout has a defect. Generally, DRC (Design Rule Checking), LVS (Layout Versus Schematic), and ERC (Electrical Rule Checking) are performed. In the ERC, for example, it is tested whether or not a current amount that can be supplied from the power wiring line is equal to or larger than a consumption current amount of the cell. That is, the current amount per unit area that can be supplied from the power wiring line is compared with the consumption current amount per unit area of the cell (Step S102). Here, when the consumption current amount of the cell is large (No at Step S102), the flow proceeds to the chip layout step (Step S101) and chip layout is corrected.
In the example shown in FIG. 2, consumption current amounts of the cells 30, 31, 32 are defined as Ib1, Ib2, Ib3, respectively and cell sizes (areas) of the cells 30, 31, 32 are defined as Sb1, Sb2, Sb3, respectively. A current amount supplied from the power wiring line 2 is defined as Ia and an area of the region A where power can be supplied is defined as Sv. In this example, the consumption current amount per unit area of the cell 30 is represented by Ib1/Sb1, the consumption current amount per unit area of the cell 31 is represented by Ib2/Sb2, the consumption current amount per unit area of the cell 32 is represented by Ib3/Sb3, and the current amount per unit area that can be supplied from the power wiring line 2 is represented by Ia/Sv. Ib1/Sb1 is smaller than Ia/Sv, and each of Ib2/Sb2 and Ib3/Sb3 is larger than Ia/Sv. In this case, layout is corrected so as to improve current supply capacity to the cells 31, 32. For example, as shown in FIG. 3, the current supply capacity is improved by arranging a new power wiring line 5. Alternatively, the cell 32 having a large current consumption amount is arranged in a layer below an upper wiring line 6 and the source voltage VDD is directly supplied from the upper wiring line 6 to the cell 32 through a contact 7. In this manner, a necessary current can be supplied to the cells 31, 32 having a large current consumption amount.
When an electrical characteristic of the semiconductor integrated circuit falls within a desired range through chip layout correction, chip layout is fixed and the chip layout phase is finished (Yes at Step S102).
However, when the new power wiring line 5 is added in the layout correction, wiring line resource of a whole of the chip deteriorates. When layout is corrected so that the cell 32 is placed in the vicinity of the upper wiring line, the placement of the cell 32 is limited by a position of the upper wiring line 6. As a result, optimization (timing driven layout) of signal wiring line between the cell 32 and the other cell 30 may not be achieved.
In order to solve the problem accompanied with such a change of the power supply capacity, for example, Japanese Patent Publication No. JP2007-258215A (refer to as Patent literature 1: corresponding to U.S. Pat. No. 7,539,964 (B2)) and JP-A-Heisei 3-16155 (refer to as Patent literature 2: corresponding to U.S. Pat. No. 5,124,776 (A)) describe methods of optimizing the current amount supplied from the power wiring line and the consumption current amount of the cell by changing sizes of the placed cells.
FIG. 4 is a plan view showing a structure of chip layout after correction of the chip layout shown in FIG. 2 according to a design method described in patent literature 1. At Step S102, when the consumption current amount per unit area of each of the cells 31, 32 is larger than the current amount per unit area that can be supplied from the power wiring line, dummy areas 33, 34 are inserted into the cells 31, 32, respectively, thereby extending cell sizes of the cells 31, 32 to Sb4, Sb5, respectively. Whereby, the consumption current amounts per unit area of the cells 31, 32 become Ib2 /Sb4, Ib3/Sb5, respectively, which each of them is smaller than the supplied current amount Ia/Sv.
As described above, according to the conventional technique, in the chip layout phase, it is need to change the arrangement of the cells and the power wiring lines or a cell size based on the current amount that can be supplied from the power wiring line. In this case, a design TAT (Turn Around Time) increases due to the optimization of the signal wiring accompanied with the layout correction, the cell displacement along with the cell extension, search of a position capable of arrangement and the like.